A Low-Power Asynchronous VLSI FIR Filter

Efficient VLSI Architectures for FIR Filters

The Finite Impulse Response (FIR) filters are widely used in many Digital Signal Processing (DSP) applications. For these applications, the low power, less area, high speed and low complexity FIR filter architectures are required. The researchers have proposed many FIR filters to meet the above design specifications. This paper is focused on the some efficient reconfigurable FIR filter architec...

A Novel Multirate Weighted Fir Filter Design Using Vlsi

A new class of FIR filtering algorithms and VLSI architectures based on the multirate approach were recently proposed. They reduce the computational complexity in FIR filtering, and also retain attractive implementation related properties such as regularity and multiply-and-accumulate (MAC) structure. In addition, the multirate feature can be applied to low-power/high-speed VLSI implementation....

Low Cost Nonrecursive Digital Filter Structures

This paper presents a novel method of hardware reduced fast FIR filter structure for parallel data processing.In general, arithmetic operation modules such as adder and multiplier modules, consume much power, energy, and circuit area. The power consumed by the adder structure is also very significant while designing a low power filter. The proposed low power multipliers and low power adders are...

Low-power and area-efficient FIR filter implementation suitable for multiple taps

This paper describes a 32-tap finite impulse response (FIR) filter with two 16-tap macros suitable for multiple taps. The derived condition for a coded coefficient and data block shows 35% savings in power consumption and 44% improvement in occupied area compared to a typical radix-4 modified Booth algorithm. According to the condition and separated shifting-accessing clock scheme, we have impl...

A low-power asynchronous data-path for a FIR filter bank